0001 ;;;
0002 ;;; Simple cassette data loader
0003 ;;; By: Daniel Tufvesson 2018
0004 ;;;
0005
0006 ;;; Monitor routines
0007 c000 mon_return: equ $c000
0008 c009 mon_pdata: equ $c009
0009 c015 mon_out4hs: equ $c015
0010 c01e mon_baddr: equ $c01e
0011 c021 mon_pcrlf: equ $c021
0012 7fe5 console_status: equ $7fe5
0013 7fe8 console_output: equ $7fe8
0014 7feb console_input: equ $7feB
0015 0002 page_register: equ $0002
0016
0017 ;;; Address of cassette interface
0018 8060 casport: equ $8060
0019
0020 ;;; Program begin here
0021 a100 org $a100
0022 a100 7e a1 35 jmp start
0023 a103 00 thresh: fcb 0
0024 a104 00 count: fcb 0
0025 a105 00 00 dsta: fdb 0
0026 a107 44 73 74 41 64 64 txt_da: fcc "DstAddr: "
72 3a 20
0027 a110 04 fcb $04
0028 a111 50 72 65 73 73 20 txt_st: fcc "Press enter and start tape"
65 6e 74 65 72 20
61 6e 64 20 73 74
61 72 74 20 74 61
70 65
0029 a12b 04 fcb $04
0030 a12c 53 74 6f 70 20 61 txt_ex: fcc "Stop at "
74 20
0031 a134 04 fcb $04
0032
0033 a135 86 f0 start: ldaa #$f0
0034 a137 97 02 staa page_register
0035 ;; Ask for address
0036 a139 ce a1 07 ldx #txt_da
0037 a13c bd c0 09 jsr mon_pdata
0038 a13f bd c0 1e jsr mon_baddr
0039 a142 ff a1 05 stx dsta
0040 a145 bd c0 21 jsr mon_pcrlf
0041 ;; Start tape
0042 a148 ce a1 11 ldx #txt_st
0043 a14b bd c0 09 jsr mon_pdata
0044 a14e bd 7f eb jsr console_input
0045 a151 81 0d cmpa #$0d
0046 a153 27 03 beq *+5
0047 a155 7e a1 ce jmp quit
0048 a158 bd c0 21 jsr mon_pcrlf
0049 a15b fe a1 05 ldx dsta
0050 ;; Start sync
0051 a15e 7f a1 03 sync: clr thresh
0052 a161 7f a1 04 clr count
0053 a164 bd 7f e5 jsr console_status
0054 a167 4d tsta
0055 a168 27 03 beq *+5
0056 a16a 7e a1 ce jmp quit
0057 a16d bd a1 da sync1: jsr cycle
0058 a170 4d tsta
0059 a171 27 eb beq sync ; resync on timeout
0060 a173 bb a1 03 adda thresh ; calc running average length
0061 a176 44 lsra ; thresh = (A + thresh ) / 2
0062 a177 b7 a1 03 staa thresh
0063 a17a 7c a1 04 inc count
0064 a17d 26 ee bne sync1
0065 ;; Calculate threshhold
0066 a17f b6 a1 03 ldaa thresh
0067 a182 16 tab
0068 a183 54 lsrb
0069 a184 54 lsrb
0070 a185 10 sba
0071 a186 b7 a1 03 staa thresh
0072 ;; Wait for sync end bit
0073 a189 bd a1 da sync2: jsr cycle
0074 a18c 4d tsta
0075 a18d 27 cf beq sync ; resync on timeout
0076 a18f b1 a1 03 cmpa thresh
0077 a192 22 f5 bhi sync2
0078 ;; Begin data load
0079 a194 6f 00 load: clr ,x ; prepare destination byte
0080 a196 bd a1 da jsr cycle ; start bit
0081 a199 b1 a1 03 cmpa thresh
0082 a19c 22 1d bhi exit ; exit when no start bit
0083 a19e 86 08 ldaa #8
0084 a1a0 b7 a1 04 staa count
0085 a1a3 bd a1 da load1: jsr cycle ; data bit
0086 a1a6 4d tsta
0087 a1a7 27 12 beq exit ; exit on timeout
0088 a1a9 b0 a1 03 suba thresh ; carry will be set on overflow
0089 ;; Shift bit into memory byte
0090 ;; (inverted data bit now in carry)
0091 a1ac a6 00 ldaa ,x
0092 a1ae 46 rora
0093 a1af a7 00 staa ,x
0094 a1b1 7a a1 04 dec count
0095 a1b4 26 ed bne load1
0096 a1b6 63 00 com ,x
0097 a1b8 08 inx
0098 a1b9 20 d9 bra load
0099 ;; End of load
0100 ;; Inform user and print end address
0101 a1bb 09 exit: dex
0102 a1bc ff a1 05 stx dsta
0103 a1bf ce a1 2c ldx #txt_ex
0104 a1c2 bd c0 09 jsr mon_pdata
0105 a1c5 ce a1 05 ldx #dsta
0106 a1c8 bd c0 15 jsr mon_out4hs
0107 a1cb bd c0 21 jsr mon_pcrlf
0108 a1ce bd 7f e5 quit: jsr console_status
0109 a1d1 4d tsta
0110 a1d2 27 03 beq quit1
0111 a1d4 bd 7f eb jsr console_input
0112 a1d7 7e c0 00 quit1: jmp mon_return
0113
0114 ;;;
0115 ;;; Get cycle time in A
0116 ;;; (0 on timeout)
0117 ;;;
0118 a1da 4f cycle: clra
0119 a1db f6 80 60 ldab casport
0120 a1de 2b 11 bmi cycle3 ; if high on entry we are out of sync
0121 a1e0 4c cycle0: inca
0122 a1e1 27 0e beq cycle3 ; timeout
0123 a1e3 f6 80 60 ldab casport
0124 a1e6 2a f8 bpl cycle0 ; wait for positive flank
0125 a1e8 4f clra
0126 a1e9 4c cycle1: inca
0127 a1ea 27 05 beq cycle3 ; timeout
0128 a1ec f6 80 60 ldab casport
0129 a1ef 2b f8 bmi cycle1 ; wait for negative flank
0130 a1f1 39 cycle3: rts
Number of errors 0